There are many types of computer memory technologies that are presently used to store computer programs and data, including dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read only memory (EEPROM), etc. Some memory technologies require electrical power to maintain the stored data (i.e. volatile memory), while others do not (i.e. non-volatile memory). Memory technologies can be read only, write once only, or repeatedly read/write.
There is an increasing demand for repeatedly read/write, non-volatile memory. The primary non-volatile memory technology presently used is EEPROM, which utilizes floating gate field effect transistor devices each holding a charge on an insulated “floating gate”. Each memory cell can be electrically programmed with one of two possible “bit values” (e.g. a “1” or a “0”) by injecting or removing electrons onto or from the floating gate. However, EEPROM memory cells are getting more difficult to scale down to smaller sizes, are relatively slow to read and program, and can consume a relatively large amount of power.
Phase change memory devices have also been known for some time. These devices use memory materials that can be electrically switched (programmed) between different structured states that exhibit different electrical read-out properties. For example, memory devices made of a chalcogenide material are known, where the chalcogenide material is programmed between a generally amorphous state that exhibits a relatively high resistivity, and a generally crystalline state that exhibits a relatively low resistivity. The chalcogenide material is programmed by heating the material, whereby the amplitude and duration of the heating dictates whether the chalcogenide is left in an amorphous or crystallized state. The high and low resistivities represent programmed bit values of “1” and “0”, which can be sensed by then measuring the resistivity of the chalcogenide material. Phase change memory devices have a high program speed (e.g. 200 ns), and exhibit great endurance and program retention.
FIG. 1 is a graphical representation of how phase change material is programmed with either a relatively high or relatively low resistivity. To amorphousize the phase change material, a short and high amplitude thermal pulse (amorphousizing thermal pulse) is applied to the phase changing material so that it reaches a temperature beyond its amorphousizing temperature TA. Once this temperature is reached, the volume of phase change material is rapidly cooled by removing the thermal pulse. So long as the phase change material is cooled faster than the rate at which it can crystallize, the phase change material is left in a relatively high-resistivity amorphous state. To crystallize the phase change material, a longer and lower amplitude thermal pulse (crystallizing thermal pulse) is applied to the phase change material so that it reaches a temperature beyond its crystallization temperature TC, and is maintained above that temperature for a sufficient time to allow the phase change material to crystallize. After such time, the thermal pulse is removed, and the phase change material is left in a relatively low-resistivity crystallized state.
FIG. 2A illustrates a memory cell 1 employing chalcogenide phase change memory material. The memory cell 1 includes a layer of chalcogenide 2 disposed between a pair of electrodes 4/6, and over thermal insulator material 8. One of the electrodes (in this case the lower electrode 4) has an increased resistivity making it a thermal heater that heats the chalcogenide layer 2 when an electrical current is passed through the electrodes 4/6 (and through the chalcogenide layer 2). FIG. 2A, for example, shows the chalcogenide 2 in its amorphous state in which the material is highly resistive. When heated by electrode 4 by a crystallizing thermal pulse, at least a portion 10 of the chalcogenide layer 2 is crystallized, as shown in FIG. 2B, which decreases the electrical resistance of the chalcogenide material. The chalcogenide 2 can be amorphousized back to its higher resistive state by applying an amorphousizing thermal pulse. The electrical resistance of memory cell 1 is read using a small electrical current that does not generate enough heat to reprogram the chalcogenide material.
It is even possible to program phase change memory material with varying degrees of amorphousization/crystallization to produce varying degrees of resistivity, so that more than two possible bit values can be stored in a single memory cell (multi-bit storage). For example, the longer the crystallizing thermal pulse, the more of the phase change material that is crystallized (i.e. the larger portion 10 becomes), and the lower the resistance of the memory material. By programming the memory material at various detectable degrees of amorphousization/crystallization, each with a different and detectable resistivity value (or range of values), multi-bit storage memory cells can be utilized.
It is known to arrange phase change memory material cells in an array configuration as schematically shown in FIG. 3, and as described in U.S. Pat. No. 6,567,296 which is incorporated herein by reference. The array includes conductive horizontal (word) address lines 12 and vertical (bit) address lines 14. Each memory cell is interconnected in series with an isolation device (i.e. PN diode) 16, and between one of the word lines 12 and one of the bit lines 14. The word and bit lines 12/14 are connected to components such as sense amplifiers, comparators, charge pumps, reference cells, pulse generators, etc. which are well known in the art and used for programming and reading the memory cells. Each memory cell 1 is associated with a unique combination of one of the word lines 12 and one of the bit lines 14. Thus, by bringing the word line and bit line associated with a selected memory cell to the writing or reading voltage(s), only that selected memory cell is programmed/read, because only the diode 16 associated with that memory cell is forward biased to allow current to pass there-through. All the remaining diodes 16 are reversed biased. During the read operation, the current flowing through the selected memory cell is compared with current flowing through a reference memory cell, to determine its programmed resistivity.
The disadvantages of this cell array configuration are that an isolation device needs to be formed for each memory cell. Further, because the memory device supplies a known voltage to the memory and reference cells, and then measures current therethrough, and any variation in resistance among the isolation devices will cause variations in the measured currents that are not attributable to the programmed resistivity of the memory cells themselves. Leakage current through the isolation devices can also be problematic.